Electronic devices, such as microprocessors, are steadily operating at faster and faster speeds. As microprocessors run at higher and higher speeds, the power delivered to the microprocessors by a power supply starts to become an issue. Power consumption has become a significant limiter in high-performance microprocessor design. The clock power of a microprocessor may be well above 60% of the entire microprocessor power. One of the largest components of power consumption is the clocking subsystem, including clock generation, distribution, and clocking power consumed in flop-flops and latches. As the clock frequency increases, many critical path delays are due to interconnects. Since more interconnects need to be pipelined, this may increase the clock power. Therefore, alternative circuit topologies to reduce the clock load need to be developed.